1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming FinFET devices with substantially undoped channel regions.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit product, device designers have greatly reduced the physical size of planar FETs over the past decades. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the planar FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of fin-formation trenches 13, three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. An insulating material 17 provides electrical isolation between the fins 14. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the gate length of the device, i.e., the direction of current travel in the device 10 when it is operational. The gate width of the device 10 is orthogonal to the gate length direction. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
In general, when forming a FinFET device, it is necessary to form a counter-doped well region in the fins 14, e.g., an N-doped well region for a PMOS device or a P-doped well region for an NMOS device. In one illustrative prior art flow, the following processing sequence was performed as it relates to the formation of such counter-doped well regions. First, an etching process was performed thorough a patterned fin-formation masking layer (not shown) to etch the trenches 13 into the substrate 12 so as to define the fins 14. Thereafter, the insulation material 17 was deposited such that it over-filled the trenches 13. Then, a chemical mechanical polishing process was performed using the patterned fin-formation hard mask as a polish-stop so as to remove excess portions of insulating material 17 positioned above the patterned fin-formation hard mask. Next, a selective etching process was performed so as to remove the patterned fin-formation hard mask and expose the upper surface of the fins 14. Then, an ion implantation process was performed to form a counter-doped well region in the fins 14. At that point, a densification anneal process (e.g., at a temperature of about 500-1200° C. for a duration of about 1-120 minutes) was performed to increase the quality of the insulation material 17 and thereby make it a better isolation structure. Thereafter, various process operations were performed to complete the device, e.g., the insulation material 17 was recessed so as to expose the desired amount of the fins 14, the gate structure was formed around the exposed portions of the fins 14 and above the recessed isolation material 17, halo implant regions and source/drain implant regions were formed in the fins 14, etc. By performing this process sequence, the portion of the fin 14 that becomes the channel region of the device, i.e., the portion under the gate structure, contains the dopant from the counter-doped well region.
Device designers are continuously in search of ways to improve device performance. For example, device designers try to increase the mobility of charge carriers (i.e., electrons for NMOS devices and holes for PMOS devices). One technique that has been employed to increase charge carrier mobility involves stress engineering. In general, various techniques are performed to create a tensile strained channel region for an NMOS device and/or a compressively strained channel region for a PMOS device. As device scaling continues, it has become apparent that the presence of the dopants from the counter-doped well region in the channel region of FinFET devices tends to limit device performance. Thus, device designers are seeking to form FinFET devices with so-called SSRW regions (Super Steep Retrograde Well regions) wherein there is little to no dopant present in the channel region of the FinFET devices.
FIG. 1B depicts one illustrative prior art technique that has been attempted to form such undoped channel regions for FinFET devices. As shown therein, the process involved initially forming the doped well regions 22 across the entire substrate 12 prior to the formation of the fins 14. Of course, using appropriate masking layers, a plurality of N-doped and P-doped well region were formed across the substrate 12. Then, an epitaxial deposition process was performed to form an undoped layer of semiconductor material 24, e.g., silicon, across the entire substrate 12. After the semiconductor material 24 was formed, then the trenches were etched into the substrate 12 to define the fins 14, the isolation material 17 was deposited and recessed, etc. Unfortunately, using the approach depicted in FIG. 1B, the “thermal budget” allowed for performing the densification anneal process is severely limited so as not to cause dopants in the counter-doped well region 22 to migrate into the previously undoped layer of semiconductor material 24. However, limiting the temperatures and/or duration of the densification anneal process means that the insulation material 17 will not be as high of a quality of insulation material as would otherwise be desired, thereby limiting its effectiveness as an isolation structure and making it more susceptible to attack and degradation when performing later processing operations.
The present disclosure is directed to various methods of forming FinFET devices with substantially undoped channel regions that may solve or reduce one or more of the problems identified above.